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THURSDAY, June 10, 2004, 10:30 AM - 12:00 PM | Room: 6A
TOPIC AREA:  SYSTEM-LEVEL DESIGN AND VERIFICATION

   SESSION 41
  Special Session: Multiprocessor SoC MPSoC Solutions/Nightmare
  Chair: Grant E. Martin - Tensilica, Inc., Santa Clara, CA
  Organizers: Grant E. Martin

  What ? (Topic) – Multi-processor System-on-Chip is the future of SoC and indeed of much of IC Design. A network of heterogeneous processors – RISCs, DSPs, ASIPs, and dedicated function blocks – interconnected by a Network-on-Chip (NoC) fabric seems destined to be a key architecture for MPSoC. However, we are a long, long way from knowing how to effectively design MPSoC and obtaining the right tools, methods and approaches. This Special session will first give an overview of MPSoC and key design problems and then have a couple of talks outlining some potential solutions.

Why ? (Motivation, Importance, Interest) - SoCs are already "MP" if we take the now classical RISC+DSP combination used in many handsets and consumer products. We currently lack effective means and tools to design even this simple combination, so the issues of how to map complex applications to MPSoC with 4, 10 or many 10's of processors is a daunting one. However, leading researchers and companies are beginning to identify solutions to key parts of this puzzle, and this special session will educate designers on what is possible and what will come.

    41.1   The Future of Multiprocessor Systems-on-Chips
  Speaker(s): Wayne Wolf - Princeton Univ., Princeton, NJ
  Author(s): Wayne Wolf - Princeton Univ., Princeton, NJ
    41.2Heterogeneous MP-SoC--The Solution to Energy-Efficient Signal Processing
  Speaker(s): Heinrich Meyr - Aachen Univ. of Tech, Aachen, Germany
  Author(s): Heinrich Meyr - Aachen Univ. of Tech., Aachen, Germany
    41.3Flexible Architectures for Engineering Successful MPSoCs
  Speaker(s): Steve Leibson - Tensilica, Inc., Santa Clara, CA
  Author(s): Steve Leibson - Tensilica, Inc., Santa Clara, CA